Experience

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Research Experience

Analog Mixed-Signal Researcher | Oct 2025 – Present

• Developing a novel toolchain that compiles custom Python-HDL hybrid to floating-gate circuits on FPAA
• Designed schematic for current-starved inverter-based envelope generator and compiled on FPAA using RASP30 toolchain
• Testing methodology to enable rapid prototyping of analog circuitry

Image Processing/Deep Learning Researcher | Aug 2025 – Present

• Converting MATLAB codebase for indoor building mapping and routing to Python (12k+ LOC)
• Optimizing adaptive routing system to accommodate varying accessibility requirements
• Overhauling image processing and annotation capabilities with keypoint deep networks & convolutional neural networks

Digital Design/Hardware Systems Researcher | May 2025 – Aug 2025

• Adapted Analog Devices' IP for JESD204B to Lattice's Holoscan sensor bridge FPGA board
• Wrote Verilog link + physical layer to stream sensor data @ 6.125 Gbps to host GPU for autonomous driving inference
• Used Lattice Radiant for comprehensive EDA toolflow (synthesis, place-&-route, timing analysis, simulation)

Georgia Tech's Chip Design Club

• Analog Mixed-Signal Design Engineer (Oct 2025 – Present): Built and verified digital inverter and single-stage amplifier in Cadence Virtuoso (schematic, layout, DRC/LVS)
• Designed, simulated, and verified ring oscillator meeting power and frequency specs (<1 mW avg. power, 500 MHz) with inverter-based buffer to drive 1 pF load
• Digital Design Engineer (Jan 2025 – Present): Engineered SystemVerilog GCD module through full stack (RTL, testbench, physical design) achieving 99.62% DUT coverage
• Designing fast divider module in SystemVerilog using Newton-Raphson & Goldschmidt algorithms with hardware-efficient LUT for initial guesses

Project Manager | Aug 2025 – Present

• Leading development of Daisy Seed based drum machine/synthesizer
• Prototyping PCBs in KiCAD for MCU, SPI/I2C networked I/O (potentiometers, audio jacks, LCD, etc), and power circuitry
• Designing novel force sensitive drum pad using mechanical keyboard switches and hall effect ICs
• Overseeing development of AI based patch generation software with integrated Daisy compiler

Team Lead + Lead Researcher | Aug 2024 – Present

• Leading mechanistic interpretability research team of 10 undergraduates and PhD candidates
• Architected framework to quantify polysemanticity of neurons in convolutional neural networks
• Developed pipeline to generate and embed feature visualizations via gradient ascent; clustered 5k+ embeddings with modified Bayesian Information Criterion
• Heading second paper exploring feature steering through generalized circuit detection in large language models

Dean's List

Georgia Institute of Technology

IEEE-Eta Kappa Nu

Honor Society Member

4.00 GPA

Perfect Academic Record