Chip Design Engineer

Synopsis

Analog Mixed-Signal Design Engineer (Oct 2025 – Present): Built and verified digital inverter and single-stage amplifier in Cadence Virtuoso (schematic, layout, DRC/LVS). Designed, simulated, and verified ring oscillator meeting power and frequency specs (<1 mW avg. power, 500 MHz) with inverter-based buffer. Digital Design Engineer (Jan 2025 – Present): Engineered SystemVerilog GCD module through full stack achieving 99.62% DUT coverage. Designing fast divider module using Newton-Raphson & Goldschmidt algorithms.